module sram_beh(//input
				clk_50M,
				n_rst,
				n_sram_we,
				n_sram_oe,
				n_sram_ce,
				n_sram_lb,
				n_sram_ub,
				sram_addr,
				//inout
				sram_dq
				);
input			clk_50M,
				n_rst,
				n_sram_we,
				n_sram_oe,
				n_sram_ce,
				n_sram_lb,
				n_sram_ub;
input[17:0]		sram_addr;
inout[15:0]		sram_dq;

reg[15:0] 		mem[1048575:0];
reg[15:0]		sram_dq_reg;

// initial begin: init_mem
// integer i;
		// mem[0]  = 16'b0000_1001_0000_1110;
		// mem[1]  = 16'b0000_0000_0000_0000;		
		// mem[2]  = 16'b0000_0000_1110_0100;
    	// mem[3]  = 16'b0000_0000_0000_0000;
		// mem[4]  = 16'b0000_0000_0000_0000;
		// mem[5]  = 16'b0000_0000_0000_0000;
		// mem[2]  = 16'b0000_0000_0000_0000;
		// mem[3]  = 16'b0000_0000_0000_0000;
		// mem[4]  = 16'b0000_0000_0000_0000;
			
// end



//initial begin
//	$readmemh("script.dat", mem);
//end

assign sram_dq = (~n_sram_oe && ~n_sram_ce && n_sram_we) ? sram_dq_reg: 16'hzzzz;


initial begin: init_mem
integer i;
	for(i = 0; i < 1048574; i=i+1)
		mem[i] = 8'd0;
end


always @(*)
	if(n_rst == 1'b0)
		sram_dq_reg = 16'h0000;
	else
		case({n_sram_oe, n_sram_ce, n_sram_lb, n_sram_ub, n_sram_we})
			5'b00000: mem[sram_addr] = sram_dq;
			5'b00001: sram_dq_reg = mem[sram_addr];
			5'b00010: mem[sram_addr][7:0] = sram_dq[7:0];
			5'b00011: sram_dq_reg = mem[sram_addr];
			5'b00100: mem[sram_addr][15:8] = sram_dq[15:8];
			5'b00101: sram_dq_reg = mem[sram_addr];
			5'b00110: ;
			5'b00111: ;
			5'b01???: ;
			5'b10???: ;
			default:
				;
		endcase
endmodule
